Ron A. Karpel
Address: 903 Avon Street Belmont, California 94002Professional Highlights:
§ Executive Vice President of SOC development – ASIC, hardware, software, production tooling, etc.
§ Expert in ASIC, CPU, DSP, and Floating Point Unit with over 27 years experience
4/02-Present Coolsand Technologies Inc. (Beijing, China and Belmont, California)
3/07-Current – Executive Vice President of Engineering
Leading worldwide software and hardware design teams of over 300 people. Responsible for cell phone chipset development projects including: baseband processors (GSM/GPRS/EDGE/3G/4G/WiMax); PMIC; integrated IC (baseband, RF transceiver, and PMIC); multimedia rich baseband processors; communication modems (GSM/GPRS/EDGE, etc). Project development includes: SOC ASIC (both analog and digital), reference PCB, software (OS, stack, PHY, MMI, multimedia, and simulation environment), production tools, customer tools, etc.
11/03-3/07 – Director of Hardware Engineering
Directed SOC ASIC chip design team. Responsible for projects which included: multimedia rich cell phone chip sets, cell phone power management IC. The design teams included: digital ASIC development, analog ASIC and chip development, ASIC backend, software OS, and software tools.
4/02-11/03 –CTO
Managed CPU hardware design. Responsible for CPU design, FPGA development board, and software development, including verification, and implementation with emphasis on low power and low cost features.
3/01-3/02 Arify Communication, Mountain View, California
Processor Architect
Responsible for CPU and DSP hardware and software development. Designed and implemented a communication coprocessor for wireless protocol. The DSP was a coprocessor to the RISC CPU and was able to accelerate GPRS PHY algorithm.
3/00-3/01 Innovision Corporation, Cupertino, California
Director Microprocessor Development
Responsible for CPU and DSP hardware and software development. Designed and implemented a development platform to run Linux operating system for TV applications.
5/96-3/00 LuxSonor, Fremont, California
Chief Scientist
Responsible for CPU and DSP hardware and software development.
10/95-5/96 IDT, Santa Clara, California
Project Manager
Responsible for CPU architecture and development.
10/94-10/95 Vantage Analysis Systems, Fremont, California
Technology Marketing Manager
Methodology expert for EDA Company. Defined tools for simulation and synthesis from the user prospective. Established market requirements through researching customer needs.
2/94 - 10/94 Sony Electronics, San Jose, California
HDL System Manager -- Managed a team of 6 engineers.
Responsibilities included developing methodology for hardware development using high-level description languages (Verilog) and synthesis. Development targeted chip and system level as well as development of all necessary diagnostic programs.
91-94 Zycad Corporation, Menlo Park and Fremont, California
Project Leader
Led 6 engineers to define, design and implement the "VIP" - VHDL Simulation Accelerator. Laid out and implemented design and verification procedures for the project. Created design hierarchy. Created simulation environment. Created test requirements and supervised testing. Tools used: Synopsys VHDL simulator and synthesis, Zycad XP simulation accelerator.
86-91 Pyramid Technology, Mountain View, California
Project Leader
Led 5 engineers to design a MIPS microprocessor based CPU board for a multi-processor system, using Verilog, Amadeus, and Synopsys design tools. Developed behavioral model of the whole system as well as simulation and verification methods.
84-86 National Semiconductor, Sunnyvale, California
Microprocessor Architecture Engineer
79-84 National Semiconductor, Tel-Aviv, Israel
Senior Test Engineer
Outside interests include: running, hiking, rock climbing, mountain climbing, traveling, landscape photography
References available on request.